The invention relates memory devices, and more particularly to a dynamic random access memory device that can operate in either a normal or a reduced power mode.
Dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices are commonly used in a wide variety of applications. One of the most common use for DRAM devices is as system memory in personal computers. The speed and capacity demands on DRAM devices continues to increase in this and other applications. However, the power consumed by DRAM devices increases with both the capacity and the operating speed of the devices. For many application, it is important to limit the power consumption of DRAM devices. For example, DRAM devices used as system memory in portable personal computers should consume relatively little power to allow a battery to power the computer over an extended period. Thus, the demands for ever increasing memory capacities and speeds are inconsistent with the demands for ever decreasing memory power consumption.
Another challenge encountered in designing DRAM devices is the need to make them usable in a wide variety of applications. It is often more desirable to adapt a single DRAM design to several applications rather than design a different DRAM for each application. This challenge can be particularly difficult when the capacity demands for DRAM devices constantly changes. It is important that a single DRAM device be usable not in state of the art applications, but also that it be xe2x80x9cbackward compatiblexe2x80x9d so it can continue to be used in more conventional applications.
The difficulties in meeting all of these design challenges is exemplified by a conventional DRAM 10, a portion of which is shown in FIG. 1. The DRAM 10 includes 4 memory banks 12a,b,c,d, each of which includes two arrays 16, 18, although some DRAMs use a lesser or greater number of memory banks with a lesser or greater number of arrays or sub-arrays in each memory bank. A single memory bank 12a,b,c,d is selected for a memory access by the output of a bank decoder 14, which receives a 2-bit bank address BA0-BA1. As is well known in the art, each array 16, 18 includes a large number of memory cells (not shown) arranged in rows and columns. An individual row is selected by activating a respective one of several row lines, collectively referred to by reference number 20, and a data bit in a selected column is read from a memory cell in the selected row and the selected column. The row lines 20 are activated by a row decoder 30, which receives a row address, typically from a memory controller (not shown). The column lines are selected by column decoders and sense amplifiers 34, which receive a column address, also typically from a memory controller. However, the row address and/or the column address may be generated from other sources. For example, the row addresses may be generated internally in the DRAM 10 for the purpose of refreshing the memory cells, as is well known in the art. The column addresses may also be generated internally in the DRAM 10 for the purpose of, for example, sequentially accessing columns of memory cells in a xe2x80x9cburstxe2x80x9d access mode.
Regardless of how the row and column addresses are generated, when each row line 20 is activated, it couples bits of data from respective memory cells in respective columns of the row of memory cells corresponding to the activated row line. A sense amplifier 34 for each column then senses the level of the data bit. Whenever a row line is activated, the sense amplifiers 34 sense the level of respective data bits in respective columns in both arrays 16, 18. When the sense amplifiers 34 are sensing data bit levels, they consume a substantial amount of power. The amount of power consumed is proportional to both the number of columns in the arrays 16, 18 and the rate at which the sense amplifiers 34 are sensing data bit levels. Thus, the power consumption of the DRAM 10 tends to increases with both higher capacity, i.e., a larger number of columns, and higher speed.
As the number of columns in the arrays 16, 18 increases, the number of data bits in each row, known as a xe2x80x9cpage,xe2x80x9d can increase beyond the number of data bits needed for a read or a write operation. For example, the DRAM 10 receives 13 row address bits (A0-A12) and 12 column address bits (A0-A9, A11, A12), to access 8K rows and 4K columns. Thus, each time a row is activated, 4K bits of data may be accessed in the xe2x80x9copenxe2x80x9d page, even though respective column addresses may select relatively few bits of data to be read from the arrays 16, 18. In fact, A11, the second highest order column address bit, will generally select either the 2K columns in the array 16 or the 2K columns in the array 18. Thus, a substantial amount of power is consumed by making data bits available from columns that will not be accessed.
In the past, the DRAM 10 has been manufactured for either a high-power application having a full page size or for a low-power application having a smaller page size. This has been done during fabrication by altering the topography of the DRAM 10 using mask options or some other alterable conductive component. For high-power applications having a full page size, each row line 20 is fabricated to extend through both of the arrays 16, 18, and the DRAM 10 is fabricated to receive 12 column address bits, A0-A9, A11, A12 to select each of the 4K columns in both of the arrays. For low-power applications having a reduced page size, one set of row lines is fabricated to extend through one of the arrays 16, and another set of row lines is fabricated to extend through the other of the array 18. One of the two sets of row lines 20 is selected by an additional row address bit, which is actually used at the most significant bit of a column address. However, since the columns in only one of the arrays needs to be selected, one less column address bit is required. Thus, in the high-power, full page size configuration, there are N row address bits and M column address bits. In the low-power, reduced page size configuration, there are N+1 row address bits and Mxe2x88x921 column address bits.
The approach described above provides some design efficiencies for the DRAM manufacturer since virtually the same design can be used for two different products. However, this approach essentially requires the DRAM 10 to be fabricated and sold as two different products, and it prevents a customer purchasing the DRAM 10 from selecting between the competing capabilities of these products after purchase. Moreover, the DRAM 10 configured for high-power and a full page size is not backward compatible in the sense that it can be used in low-power applications. The DRAM 10 configured for high-power and a full page size is not backward compatible for low-power, reduced page size applications because the number of row and column address bits would be incompatible.
There is therefore a need for DRAM and method of using same that allows the DRAM to be configured by a user for either high-power, full page size operation or low-power, reduced page size operation with the need for extra row address bits.
A memory device includes an array selecting system that selectively couples row activate signals to either or both of two memory cell arrays without causing significant time penalties. A mode select circuit is programmed to generate a mode select signal that is indicative of operation in either a first or a second mode. The array selecting system receives the mode select signal and an array select signal, which corresponds to a most significant bit of a column address. However, the array select signal is applied to the memory device before the column address is applied, such as at the same time a row address is applied to the memory device. If the mode select signal indicates operation in the first mode, the array select circuit allows the row activate signal to be applied to a row line in both the first and second arrays. If the mode select signal indicates operation in the second mode, the array select circuit allows the row activate signal to be applied to a row line in only one of the arrays depending upon the state of the array select signal. A column control circuit receiving the mode select signal and the array select signal may also selectively de-power sense amplifiers coupled to one of the arrays that is not receiving a row activate signal.